1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device that includes a silicon oxide layer, and more particularly, to a method of fabricating a semiconductor device that includes dual spacers that include a silicon oxide layer formed on sidewalls of a gate line patterns.
2. Description of the Related Art
In semiconductor memory devices, especially in DRAMs having a unit cell with one transistor and one capacitor, a plurality of gate lines serving as conductive lines for transferring signals to gate electrodes of transistors, which form memory cells, may be formed on silicon substrates. These gate lines may form spacers on the sidewalls of gate line patterns to provide insulation between peripheral devices and between direct contacts (DC) and buried contacts (BC) of DRAMs. The spacers may be formed of an insulating material, such as silicon oxide (SiO2) and silicon nitride (Si3N4). Such insulating materials may improve insulating efficiency and reduce deformation which may occur during subsequent thermal processes.
In conventional methods of forming single spacers on sidewalls of gate line patterns using silicon nitride as a spacer material, a gate insulating layer, a gate conductive layer, and an insulating gate mask layer may be sequentially deposited on a silicon substrate. Gate line patterns may be formed by a photolithography process. Next, a silicon nitride layer may be blanket deposited on the silicon substrate. The gate line patterns and the silicon nitride layer may then be etched until the gate mask layer and the surface of the silicon substrate are exposed. As a result, silicon nitride spacers may be formed on the sidewalls of the gate line patterns.
However, because the difference between the etching selectivity of the silicon nitride layer and the etching selectivity of the silicon substrate is small, the surface of the silicon substrate may be damaged when the silicon nitride layer is etched. In addition, damaged portions of the silicon substrate may cause leakage currents to storage electrodes of capacitors. As a result, refresh characteristics may deteriorate.
For example, when etching a silicon nitride layer to form spacers on the sidewalls of gate line patterns in a RAM device, e.g. a dynamic RAM (DRAM) or a static RAM (SRAM), static refresh varies depending on the thickness of the oxide layer remaining on the silicon substrate. Thus, when the thickness of the remaining oxide layer is small, characteristics of the static refresh may deteriorate because of damage which may occur during a dry etching process.
In addition, when dry etching a silicon nitride layer to form spacers in a RAM device, e.g., SRAM or DRAM, or a logic device, the silicon substrate may be damaged. In addition, fluoric elements which may be included in a dry etching etch gas may combine with the surface of the silicon substrate. As a result, a metal silicide may be formed on an active region of the silicon substrate and defects may occur. Further, when both a metal gate and a salicide process are used, a metal layer of the metal gate may be dissolved by chemical solutions used in a wet cleaning or a metal strip process, e.g., an SCI or an H2SO4/H2O2 solution, even when the metal gate is encapsulated by a silicon nitride spacer.
In a conventional method of forming dual spacers on gate line patterns, a gate insulating layer, a gate conductive layer, and an insulating gate mask layer may be sequentially deposited on a silicon substrate and gate line patterns may be formed by a photolithography process. A silicon oxide layer and a silicon nitride layer may then be sequentially deposited on the silicon substrate and the gate line patterns. The silicon nitride layer may be etched until the silicon oxide layer is exposed, and a silicon nitride layer may remain on the sidewalls of the gate line patterns. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls of the gate line patterns.
In such dual spacers, a difference between the etching selectivity of the silicon oxide layer and the etching selectivity of the silicon nitride layer may be large. Therefore, the silicon oxide layer may operate as an etch stopping layer. In addition, the silicon oxide layer may be removed by a subsequent cleaning process and dual spacers may be formed with a reduction in damage to the silicon substrate.
Although a gate line may be formed of a conductive layer which may include a polysilicon layer and a metal silicide layer, a material having a low resistivity may be used as a conductive line to reduce signal delay time. In order to reduce resistance, the metal gate line may include a pure metal layer such as tungsten, molybdenum, titanium, cobalt, nickel, or tantalum instead of the metal silicide layer. A stacked structure of tungsten/tungsten nitride/polysilicon is one example of using a metal layer as a portion of the gate line.
However, when a conventional method of forming dual spacers is applied to a metal gate line, problems with oxidizing the surface of an exposed metal layer, e.g., tungsten, molybdenum, titanium, cobalt, nickel, or tantalum, may occur when depositing a silicon oxide layer after the gate line patterns (including a pure metal layer of tungsten) are formed. The oxidization of the metal layer may cause a reduction of an effective sectional area of a conductive line. As a result, the resistance of the conductive line may increase and the vertical profile of the gate line pattern may deteriorate.
FIG. 1 is a scanning electron microscope (SEM) photograph illustrating a deposition profile of a silicon oxide layer in a semiconductor device fabricated by a conventional method. The gate line patterns in FIG. 1 may be formed by sequentially depositing and patterning a gate oxide layer, a polysilicon layer, a tungsten nitride layer, a tungsten layer, and a silicon nitride layer. The silicon oxide layer may be formed on gate line patterns by simultaneously a silicon source gas (e.g., SiH4) and an oxygen source gas (e.g., N2O). In the example illustrated in FIG. 1, after the silicon oxide layer was formed on the gate line patterns, a polysilicon layer was formed on the entire surface of the substrate having the gate line patterns to a thickness of approximately 2000 Å and the substrate was cut along a vertical direction. The cut substrate was then processed with Hf to selectively etch the silicon oxide layer faster than either the polysilicon layer or the other material layers of the gate line patterns. Black portions along the gate line patterns indicate the silicon oxide layer.
As shown in FIG. 1, when the silicon oxide layer was formed, the tungsten layer may be oxidized and the area of the tungsten layer may be reduced. In addition, oxidized portions of the tungsten layer may protrude from the gate line patterns. Thus, the width of the tungsten layer may be reduced and the vertical profile of the gate line patterns may be of poor quality.